A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Abstract To meet the demand of low bit error rate and high bandwidth for high-speed links, a reliable 112 Gb/s four-level pulse amplitude modulation (PAM4) transceiver design scheme with adaptive threshold voltage decision feedback equalizer is proposed in this paper. In scheme, three continuous time linear equalizers (CTLEs) at front end receiver are used to compensate high-frequency, mid-frequency low-frequency signals, respectively, variable gain amplifier (VGA) saturation (SatAmp) scale signal amplitude. addition data samplers, four auxiliary samplers also adaptation. The sign-sign least mean squares algorithm uses offset between sampler side drive reference converge constellation level, thus ensuring that eye diagram PAM4 received has equal spacing constant signal–noise ratio eyes vertical direction. addition, DFE signaling allows better adapt channel achieve performance. simulation results show can up 25 dB loss an average height 59.6 mv width 0.27 UI 10 −12 under condition 3-tap feedforward (FFE) transmitter.